FIG. 7 is a cross-sectional view showing the construction of a prior art high-frequency and high power semiconductor device. The semiconductor device starts with a GaAs semiconductor substrate 1. Elements 2 such as FETs are produced in the surface of the substrate 1. Via-holes 3 are produced through the substrate so as to electrically connect the front surface and the rear surface of the substrate 1. A metal layer 3a comprising such as Au is produced at the wall surface of the via-hole 3. The rear surface of the substrate 1 is fixed onto a plated heat sink (PHS) 7 comprising Au for such as radiation of heat. Curvature of the chip is indicated by .delta. and the length of the longer edge of the curved chip is indicated by l.
The semiconductor device is fabricated as follows.
First of all, elements 2, such as FETs are produced at the surface of a semiconductor substrate 1 and via-holes 3 are also produced through the substrate 1. Thereafter, the semiconductor substrate 1 is polished at its rear surface until the thickness of substrate 1 is about 30 microns, so that the metal layer 3a in the via-hole 3 is exposed its bottom. A PHS 7 of about 40 microns thickness is produced at the rear surface side of substrate 1 by Au electroplating. Thereafter, the substrate 1 and the PHS 7 are cut by a dicer or etching and high-frequency and high power semiconductor chips are obtained as semiconductor devices.
In such a semiconductor device, the PHS 7 radiates heat generated at the active semiconductor element 2 such as an FET which is produced at the surface of semiconductor substrate 1. The PHS 7 also reinforces the thin semiconductor substrate 1 thereby to ease the handling of the chip. In this semiconductor device, however, curvature of chip arises due to the difference between the linear thermal expansion coefficients of the materials, i.e. the substrate 1 and the Au PHS 7.
In an example where the substrate 1 is a GaAs layer about 30 microns thick and the PHS 7 is an Au layer about 40 microns thick when the following bimetal formula is used with a die-bonding temperature of 300.degree. C., the curvature .delta. and the length of chip longer edge l are in a relation shown in FIG. 8, where the curvature .delta. significantly increases with the increased length of chip longer edge l. ##EQU1## here, .alpha.1: linear thermal expansion coefficient of GaAs (6.times.10.sup.-6 [deg.sup.- ])
.alpha.2: linear thermal expansion coefficient of Au (14.times.10.sup.-6 [deg.sup.-1 ]) PA1 E.sub.1 : Young's modulus of GaAs (8.55.times.10.sup.11) PA1 E.sub.2 : Young's modulus of Au (7.8.times.10.sup.10) PA1 .DELTA.T: temperature change (300.degree. C.-25.degree. C.=275 deg) PA1 .delta.=R(1-cos.theta.) PA1 .theta.=tan.sup.-1 (L/2R)
And the curvature .delta. is calculated by the formula as follows.
More concretely, when the length of the chip longer edge l is larger than 2.5 mm in the prior art semiconductor device with the above-described conditions die-bonding and wire-bonding are difficult when mounting the chip onto a chip carrier and as the contact area between the chip and the chip carrier is largely reduced. This significantly deteriorates the heat radiating characteristics, resulting in undesired RF characteristics.
As a measure for preventing such curvature of a chip, Japanese Published Patent Application 61-23350 discloses a structure in which a hollow part is produced at the rear surface of a semiconductor substrate so that the semiconductor substrate directly opposite an active region is thinner than the periphery thereof and a metal fills this hollow part. In this case, however, the radiating region at the rear surface side of the substrate is narrowed and the radiating effect is significantly reduced.